Come join Intel's Design Engineering Group responsible for designing Client SoCs that make up more than half of Intel's annual revenue. We envision the future of computing and design for the next generation of Laptops and desktop computers.
We are looking for an SoC (System on Chip) Standard Cell library design engineer, ready to research, design, develop, and test lead Intel designs as we reimagine how to build SoCs at Intel and in the semiconductor industry.
This role is within Intel's highly regarded Devices Development Group headquartered in Portland, Oregon with additional sites in Austin, Texas and Penang, Malaysia.
Our bold purpose as a company is to create world changing technology that enriches the lives of every person on earth and this role is instrumental in furthering our mission to shape the future of technology.
As a member of the design team, your responsibilities will include, but not be limited to:
Validate, build, and characterize standard cell libraries.
Provide customer support for multiple CEG projects for library, including Verilog, liberty, and library TFM.
Work on extraction, simulation and PPA studies/experimentation.
The ideal candidate will also have the following skills in addition to the qualifications listed below:
High motivation and results orientation
Strong problem-solving skills
Excellent interpersonal skills, including written and verbal communication.
Teamwork, negotiation, and presentation skills
You must possess the below minimum qualifications to be initially considered for this position Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications:
The candidate must possess a Bachelor's in electrical or computer Engineering and 5+ years of experience - OR - Master's degree in electrical or computer Engineering and 3+ years of experience:
Your experience must be in the following:
5 years of experience related to Stdcell (Standard cell) Libraries.
Ability to run circuit simulations.
Preferred Qualifications:
Skill for automation using Python and/or TCL.
Experience with block-level APR design.
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